For most of semiconductor history, the package was what happened after the important work.

Engineers designed a chip, a fab printed its transistors, and a less celebrated part of the industry protected the finished die and connected it to a circuit board. The package was necessary, difficult and economically disciplined, but the conceptual center of computing remained the monolithic chip.

AI hardware has broken that hierarchy.

The largest processors now depend on multiple pieces of silicon placed beside or above one another, linked through dense wiring and paired with stacks of high-bandwidth memory. Power must enter. Heat must leave. Signals must cross boundaries quickly enough that separate dies behave like one machine. The object that makes those negotiations possible is the package.

It is no longer a container for the computer. Increasingly, the package is the computer.

The reticle forced a change

A lithography machine projects a pattern across a limited area. That exposure field places a practical ceiling on how large a single manufactured die can be. Designers can approach the boundary, but larger dies are expensive for another reason: a defect that ruins one portion can discard the whole piece.

Chiplets change the unit of composition. Instead of printing every function on one enormous die, a system can combine smaller dies built for different jobs. Leading-edge logic can sit beside older-node input/output circuitry. Memory can be manufactured in a process optimized for memory. Analog, radio and photonic components can join digital logic without forcing all of them through one compromised process.

This is heterogeneous integration: make each component where it makes sense, then build a system at package scale.

The economic attraction is straightforward. Smaller dies can yield better. Proven components can be reused. A product family can change one compute tile without redesigning every interface. But none of those advantages is free. A boundary that disappeared inside a monolithic chip returns as a physical interface with latency, energy, alignment and reliability costs.

Advanced packaging is the engineering required to make those costs small enough.

Wires become architecture

On a circuit board, chips communicate over relatively long, sparse connections. Inside an advanced package, silicon interposers, bridges, redistribution layers and direct bonds can create far denser paths. That abundance changes system design.

High-bandwidth memory illustrates the point. Instead of placing conventional memory modules farther away on a board, manufacturers stack memory dies and place the stacks close to the processor. Wide interfaces move more data at lower energy per bit. The package becomes a carefully planned neighborhood: compute tiles, memory stacks, fabric, power delivery and cooling compete for area and access.

This is why a shortage of packaging capacity can constrain AI systems even when leading-edge wafers exist. A finished logic die without the right interposer, memory and assembly process is not a sellable accelerator.

TSMC’s 2025 annual report describes advanced packaging and 3D stacking—including CoWoS, InFO and SoIC—as central to energy-efficient computing. It also reports qualification of a CoWoS solution using an interposer 5.5 times the maximum reticle area, with volume production planned for 2026.6 The package is expanding beyond the dimensions that originally pushed designers toward chiplets.

Scale-out is happening inside the box.

Heat is a first-class design input

Putting more active silicon closer together reduces communication energy and creates a harder thermal problem. Logic produces concentrated heat. Memory has its own temperature limits. Adhesives, underfills, substrates, copper and silicon expand differently as they warm. Repeated cycles create stress at microscopic connections.

The industry’s “soft” materials—polymers used to bind, insulate and protect components—now determine whether an advanced device remains flat, aligned and intact. NIST notes that some new packaging materials can take 10 to 25 years to reach production, while current systems demand better measurement of cure, shrinkage, moisture behavior and mechanical stress.3

This is a useful correction to the way computing progress is narrated. A new architecture may be drawn as clean blocks and arrows. Its performance can ultimately depend on how a polymer changes shape after thousands of thermal cycles.

Cooling is similarly architectural. Heat sinks mounted above a package are giving way to more integrated approaches: cold plates, liquid channels, backside power delivery and designs that account for thermal paths from the first floorplan. A chiplet placed in the wrong location can turn a logical success into a cooling failure.

The package designer therefore works across electrical, mechanical, thermal and manufacturing domains at once.

Alignment becomes yield

Hybrid bonding can connect dies through extremely fine copper contacts while bonding their surrounding surfaces. The tighter the pitch, the greater the potential bandwidth—and the smaller the tolerance for particles, topography and misalignment.

NIST’s 2026 work on hybrid-bonding-ready structures focuses on measuring mechanical behavior at nanoscale copper pads.4 This sounds distant from computer architecture until one failed bond severs a critical link inside a package containing several expensive dies.

Manufacturing yield now has layers. Each chiplet must be known-good before assembly. The substrate and interposer must be sound. Bonding must succeed across many interfaces. The package must survive test, thermal cycling and field operation. As more components are combined, hidden defects become more expensive.

Test cannot remain an inspection at the end. Designers need observability built into chiplets and interfaces, standardized ways to identify failures, and models that connect process measurements to eventual reliability. NIST’s semiconductor standards report identifies thermal management, defect inspection, alignment and data exchange as continuing metrology gaps.7

In advanced packaging, measurement is production infrastructure.

From company product to ecosystem

Chiplets are most powerful when a designer can combine components from different suppliers. That requires more than a physical connector. The parts must agree on protocols, power states, initialization, security, test and management across their useful lives.

The Universal Chiplet Interconnect Express consortium is building one such interface. UCIe 2.0 added system-level support for manageability, test and debug across multiple chiplets; UCIe 3.0 extends the standard further.5 The ambition is an ecosystem in which dies can become composable intellectual property in physical form.

Interoperability will arrive more slowly than the metaphor suggests. A chiplet is not a USB accessory. It operates at extreme speed and density, and its behavior is entangled with the package around it. Commercial trust matters too: vendors must expose enough information for integration without giving away the designs that differentiate them.

The likely transition is layered. Large companies first compose their own internal chiplets. Close partners qualify components together. Standards stabilize around the interfaces that prove repeatable. Open marketplaces emerge only where electrical compatibility, supply assurance, security and liability can be made legible.

The winners may be less open than enthusiasts hope and more modular than incumbents expect.

National strategy moves downstream

Governments spent the first phase of semiconductor policy focused on fabs. That was reasonable: leading-edge fabrication is capital intensive, geographically concentrated and foundational. But a wafer fabricated domestically and shipped abroad for critical assembly remains part of an incomplete supply chain.

In January 2025, the U.S. Department of Commerce finalized $1.4 billion in awards under the National Advanced Packaging Manufacturing Program for substrates, equipment, materials and a packaging piloting facility.1 The program’s premise is that research must reach validated, scalable manufacturing rather than stop at a laboratory demonstration.

That distinction is essential. Packaging innovation needs pilot lines where designers can learn what survives production. It needs shared tools for companies that cannot build a full line themselves. It needs workforce spanning materials science, mechanical engineering, process control and electronic design automation.

The strategic asset is not one patented bonding technique. It is the loop that moves a new system from design to assembly, measurement, failure analysis and redesign.

Design tools have to cross the package boundary

Electronic design automation grew around distinct objects: chip, package and board. Each had its own models, teams and sign-off process. Chiplets blur those borders. A decision about die placement changes wiring delay, power integrity, thermal gradients, mechanical stress and the routes available on the substrate.

Sequential handoffs are poorly suited to that coupling. By the time a thermal team discovers a hotspot, the logical partition may be fixed. By the time package routing exposes a congestion problem, the chiplet interfaces may already be committed. The cost of iteration rises precisely when more iteration is required.

The next toolchain needs shared models at several levels of fidelity. Early exploration should compare architectures quickly without pretending to know manufacturing detail. Later analysis should replace estimates with foundry, substrate and material data. Results should remain traceable so a designer can see which assumption changed a conclusion.

This is also where supply-chain reality enters design. A theoretically optimal stack may depend on one memory configuration, interposer size or bonding line with limited capacity. Package-aware planning should expose qualified alternatives and the performance cost of using them. Resilience can then be designed rather than discovered during allocation.

Security crosses the same boundary. A system assembled from several chiplets needs ways to establish identity, authenticate firmware and manage components with different trust histories. Test access that helps diagnose a failed die can become an attack surface if it remains exposed in the field.

The “system technology co-optimization” discussed across the industry is therefore partly organizational. It asks companies and disciplines to reveal constraints early enough for the whole system to improve. Better software can provide the shared object, but commercial agreements and technical standards determine what data can enter it.

The package becomes truly programmable when designers can reason about performance, manufacturability, security and supply in the same loop.

Where the new tools belong

As the package becomes a system, its software layer grows. Builders have room to work on:

  • package-aware architecture exploration before expensive physical design;
  • thermal and mechanical digital twins tied to real process measurements;
  • known-good-die test and provenance;
  • chiplet identity, security and lifecycle management;
  • interoperable design data across electrical and mechanical tools;
  • inspection systems for buried defects;
  • scheduling and yield optimization across multi-vendor assembly;
  • reusable interface blocks and qualification evidence;
  • cooling designed as part of compute orchestration rather than facility plumbing.

The most valuable tools will close disciplines that currently hand work to one another. A thermal result should be able to change a floorplan. A metrology signal should update a yield model. A field failure should become a test condition for the next revision.

The edge of Moore’s Law is organizational

It is common to say Moore’s Law is ending. A more precise observation is that progress is moving outward.

Transistor scaling continues, but the performance of a useful system increasingly depends on the relationships among dies, memory, interconnect, power, cooling, materials, assembly and software. The engineering object has widened. So has the industrial coalition needed to build it.

This makes advanced packaging an unusually rich frontier. It combines frontier physics with factory operations, standards with proprietary advantage, and national strategy with microscopic surfaces. The details resist abstraction: a system can fail because a model was wrong, because a supplier slipped, or because two materials expanded by different amounts.

The chip was once the place where integration created advantage. That advantage has moved into the package—and with it, the next generation of computers.